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In this paper, we present a three-dimensional graphene foam made of few layers of CVD grown graphene as a scaffold for growing cardiac cells and recording their electrical activity. Our results show that graphene foam not only provides an excellent extra-cellular matrix (ECM) for the culture of such electrogenic cells but also enables recording of its extracellular electrical activity in-situ. Recording...
To mine large digital libraries in humanistically meaningful ways, we need to divide them by genre. This is a task that classification algorithms are well suited to assist, but they need adjustment to address the specific challenges of this domain. Digital libraries pose two problems of scale not usually found in the article datasets used to test these algorithms. 1) Because libraries span several...
This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 mum2. Vmin operation down to 0.6 V in a 16 Mb SRAM array test vehicle has been demonstrated. Aggressive ground rules are achieved with 193 nm immersion lithography. High performance is enabled by high-k/metal gate plus innovation on strained silicon elements including embedded SiGe and dual stress...
For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and drive current over our best poly-gate 45 nm-node nMOSFET with SMT and tensile liner stressors. In addition, eSi:C showed better scalability than SMT plus tensile liner stressors from 380 nm to 190 nm poly-pitches.
We report a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. We identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (Csub) of ~1.0%, high performance nFETs with SiC stressors demonstrate ~9% enhanced Ieff and ~15% improved Idlin against the...
This paper presents for the first time (110) PMOS characteristics without Rext degradation, allowing investigation of fundamental mobility and demonstration of drive current Ion in excess of 1mA/mum at Ioff =100 nA/μm.
This work demonstrates that the 2?? mobility advantage of (110) PMOS over (100) PMOS is maintained down to 190nm poly-pitch for devices under compressive stress. (110) PMOS with 3.5GPa compressively stressed liners demonstrate strong channel drives with Ion=800 ??A/??m at Ioff=100nA/??m (Vdd=1.0V) for 190nm poly-pitch, the highest reported to date for 45-nm-node (110) PMOS using conventional gate...
Hybrid-orientation technology (HOT), a novel planar CMOS approach that fabricates NMOS on (100) silicon surface and PMOS on (110) silicon surface to take advantage of the highest carrier mobilities on these surfaces, is reviewed. HOT module process flow, defects formed during the HOT module, HOT CMOS performance enhancement and its layout dependence, as well as the high Rext issue for (110) PMOS are...
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific...
We have investigated the impact of laser spike anneal (LSA) on the performance of ultra-thin SOI MOSFETs. LSA was found to significantly reduce the parasitic external resistance in UTSOI devices. Reduced external resistance in conjunction with improved gate activation resulted in a substantial improvement in nFET performance. A conventional spike RTA followed by LSA at 1300C enhances nFET drive current,...
We report for the first time, the effect of stress memorization (SM), and the combined effects of SM and dual stress liner (DSL) on high performance fully-depleted ultra-thin channel devices with a raised source/drain architecture and channel thickness of 18nm. SM results in significant drive current and mobility enhancement, comparable to that obtained using the DSL approach. Stress transfer to the...
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting...
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