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Most DRAM interfaces such as GDDR5 and DDR3 use parallel single-ended signaling due to pin-count restriction and backward compatibility. Notwithstanding poor signal and power integrity issues, GDDR5 speed reached beyond 5Gb/s in recent years by utilizing data bus inversion, error-detection coding, data training and channel equalization. However, channel crosstalk is becoming a major barrier to further...
This paper describes a 1 Gbit GDDR5 SDRAM with enhanced bank access flexibility for efficient data transfer in 7 Gb/s per pin IO bandwidth. The enhanced flexibility is achieved by elimination of bank group restriction and reduction of bank to bank active time to 2.5 ns. The effectiveness of these key features is verified by system model simulation including memory and its controller. To realize the...
7 Gb/s/pin operation without bank group restriction in a GDDR5 SDRAM is achieved by skewed control logic and current-mode I/O sense amplifiers with regular calibration from replica impedance monitors. The bank-to-bank active time is shortened to 2.5 ns by a FIFO-based BLSA enabler, 2.0 ns latency VPP generator and active jitter canceler. The chip is fabricated in a 50 nm DRAM process in a 61.6 mm2...
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