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A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various...
This study discusses variability of the high and low resistance states (HRS and LRS, respectively) during the pulse cycling of the cross-bar 1T1R HfO2 based RRAM devices. Read current variation in LRS is found to follow a normal distribution while in the HRS, it is described by the log-normal dependency. It has been identified that the endurance degradation primarily occurs due increasing resistance...
Lower operation current and voltage are strongly required for scaled RRAM devices with high density memory cell arrays. As the lower operation current reduces the size of the conductive filament, stable high speed endurance performance of RRAM device becomes a challenging issue. In this work, for the first time, we demonstrate 1μA, +/−1V bipolar switching and a 100x reduction of the high-resistance-state...
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