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In this paper, we present a low dropout voltage regulator (LDO) which can be programmed to generate four output voltages (3.3 V, 2.5 V, 1.8 V, and 0 V) by the external control signals. Between the error amplifier and the power transistor, we place a simple buffer so that the power supply rejection (PSR) of LDO can be improved. The design specification of the maximum load current is 100 mA. The proposed...
In this paper, we propose an approximate square criterion for H.264/AVC intra mode decision. The sum of square difference (SSD) criterion achieves the best video quality but takes much high computation due to the square operation. A sum of approximate square difference (SASD) criterion is proposed to maintain the video quality and reduce the computation. By applying the characteristic of the SSD criterion,...
This paper demonstrates a 0.8-V, 9-bit, 20-MS/s pipelined ADC with only 0.58 pJ-Volts/step. A novel circuit architecture which merges opamp-sharing with loading-free structure is proposed. Such mechanism effectively reduces the number of opamps as well as the capacitive loading. In addition, an inverse-flip-around sample-and-hold with unity-feedback factor is employed which further reduces the power...
In this paper, an algorithm for improving image quality with original optimized rate-distortion extraction mechanism in the scalable extension with H.264/AVC is proposed. In our algorithm, the importance of the first MGS (medium grain scalability) layer was thought higher, thus we carry more weight on it when estimating quality information and assigning priority IDs. In our experiment, the PSNR (peak...
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