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We comprehensively study three types of radiation-hardened flip-flops: DICE for SEU-hardening, temporal for SET-hardening, and Triple-Modular-Redundancy for SEU-cum-SET-hardening. Our study includes their trade-offs of circuit/radiation-hardness attributes. We find that DICE flip-flops remain the most competitive.
We propose a novel asynchronous logic (async) quasi-delay-insensitive (QDI) sense-amplifier half-buffer (SAHB) cell design approach, with emphases on high operational robustness, high speed, and low power dissipation. There are five key features of our proposed SAHB. First, the SAHB cell embodies the async QDI 4-phase ($4\phi )$ signaling protocol to accommodate process-voltage–temperature variations...
We propose a novel dynamic voltage scaling (DVS) pipeline with three significant attributes. First, it features a finegrained DVS which innately attempts to power most of the circuits therein at low voltages, and when the speed is beneath the requirement, to scale up the voltage. Second, it supports fasttransition DVS within one-and-a-half clock duration per operation, and its operation remains error-free...
Self-Adaptive VDD Scaling (SAVS) technique achieves power/energy reduction by dynamically scaling VDD for the prevailing conditions. However, when applied in sub-threshold (sub-Vt) region, robustness issues need to be addressed due to the severe delay uncertainty associated with sub-Vt Process, Voltage, and Temperature (PVT) variations. To ensure robustness for sub-Vt SAVS, we adopt the asynchronous-logic...
In this paper, a fine-grained power gating technique for an asynchronous-logic pipeline stage is proposed using locally controlled gating transistors. The proposed power gating technique is implemented with minimal control overheads (one additional inverter per pipeline stage for driving PMOS Gating) and delay overheads (within 15% more than the conventional asynchronous-logic pipeline stage). Different...
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