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A 1.2V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC) based on double-sampling technique is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme...
A 12-b 40-MSamples/s low power CMOS pipelined analog-to-digital converter is described. A novel switched-capacitor multiply-by-two amplifier with an accurate gain of two is proposed for pipelined ADC. The proposed architecture requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error due to capacitor-mismatch and also provides a better power...
A new switched-capacitor multiply-by-two amplifier with an accurate gain of two is presented. The proposed architecture requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error due to capacitor-mismatch and also provides a better power efficiency. Monte-Carlo simulation results are presented to confirm the feasibility of this new technique,...
A 10-b low-voltage CMOS pipelined analog-to-digital converter is described. A low-voltage technique is proposed for pipelined ADC that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough...
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