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Given the recent difficulty in continuing the classic CMOS manufacturing density and power scaling curves, also known as Moore's Law and Dennard Scaling, respectively, we find that modern complex system architectures are increasingly relying upon accelerators in order to optimize the placement of specific computational workloads. In addition, large-scale computing infrastructures utilized in HPC,...
We have designed a trigger test board (TTB) to test the local trigger board (LTB) for the Daya Bay reactor neutrino experiment, which is aimed to measure the neutrino mixing angle sin22θ13with a precision down to 1% level at 90% C.L‥ In this experiment, there are three modular detectors, which are located in two near halls and one far hall. The modular detector consists of three types of sub-detectors:...
This paper presents a hardware implementation method for the SubBytes and InvSubBytes transformations of the AES in view of foregoing look-up tables (LUT) having unbreakable delay. In addition, the transformations would be exceeding complex in hardware if affine transformation in Galois Field GF(28) is employed. It will lead to slow computing speed and high cost of source. Hence decomposing method...
We show that the ideal spectrum granularity in dynamic flexible grid networks to achieve best blocking performance is determined by the greatest common factor of spectrum widths of all mixed-rate signals.
Prediction, including intra prediction and inter prediction, is the most critical issue in H.264 decoding in terms of processing cycles and computation complexity. These two predictions demand a huge number of memory accesses and the total decoding cycles. In this paper, an efficient hardware architecture for real-time implementation of intra and inter predictions algorithm used in H.264 video coding...
In this paper, an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 video coding standard is adopted. The hardware design is based on a novel organization of the intra prediction equations. Compared with conventional architecture, intra predict efficiency is enhanced. The Verilog RTL is verified to work at 103 MHz in a Xilinx II FPGA.
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