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As a result of population aging, remote electrocardiograph (ECG) monitoring systems have increasingly gained attention. The traditional ECG signal acquisition system has many limitations. This paper presents a high-precision sigma-delta modulator for ECG signal acquisition. The circuit is implemented in a SMIC-EE 0.18 µm process. Simulation results indicate that the signal-to-noise ratios with and...
We introduce a microwave imaging technique that integrates the asynchronous particle swarm optimization (APSO) into through wall imaging (TWI) within the finite difference time domain (FDTD) model of the inverse scattering problem. The forward scattering equations are solved by the FDTD method is employed to calculate the scattered E fields. Based on the scattering fields, the inverse scattering problems...
In recent years, the FPGA performance requirements are changes in the evolution. From the past a static schedule way, development tasks are running to the dynamic scheduling system. This study proposed FPGA dynamic reconfigurable scheduling and placement base on TGFF generated Random standard schedule and Grey relation of grey system. The scheduling method accords to the placement of strategy objectives...
Mobile and ubiquitous computation of embedded system exacerbates energy consumption. In this work, we propose minimum energy path (MEP) approach to improve energy efficiency for embedded system. The MEP adopts path-based strategy to constructs a set of path class. Each path comprises the number of tasks that will be sequentially determined the role depending on the energy consumption. As a result,...
Heterogeneous embedded systems are much more diverse in hardware architectures than ever before for processors and peripherals. On the other hand, software deployments are also varied such as service-oriented architecture (SOA), open systems interconnection (OSI) and component-based software development (CBSD). The diverse architectures of hardware and software cause problems corresponding to time-to-market,...
This paper aims at developing grey relational clustering for FPGA placement. The proposed GRAP (Grey Relational Clustering Apply to Placement) algorithm was combined with grey relational clustering and CAPRI algorithm to successfully solve FPGA placement design problem. Experimental results demonstrate that the GRAP compares the Hilbert, Z and Snake with BB cost function in space filling curve. The...
Embedded systems with communicating and computing ability and multimedia functions work to every corner of daily life. However, the diverse architectures of embedded systems cause problems corresponding to reuse, portability and dependability. Middleware is a set of software that executes between operating system and application to solve stated problems. The advantages include unified interface, scalable...
This work aims at developing grey relational grade for minimal wire length FPGA placement to follow-up the FPGA routing work. The proposed GRAP (Grey Relational Grade Apply to Placement) algorithm was combined with grey relational clustering and CAPRI algorithm to construct a placement netlist to successfully solve minimal wire length in FPGA placement design problem. After the grey relational grade...
This work studies how the architectural parameters of LUT-based field programmable gate arrays (FPGAs) are related to the LUT cluster size N and input number k A novel algorithm is proposed to combine grey decision-making approach for solving the problem of FPGA performance. Experimental results demonstrate that the algorithm improves the DAO map+T-VPack delay by 7.27% and reduces the SMAC total of...
This paper reports a two-dimensional time-domain inverse scattering algorithm based upon the finite-difference time domain method for determining the shape of perfectly conducting cylinder. Finite difference time domain method (FDTD) is used to solve the scattering electromagnetic wave of a perfectly conducting cylinder. The inverse problem is resolved by an optimization approach and the global searching...
Due to the advanced lithography technologies in current semiconductor process, X-architecture has been widely used in VLSI physical design. The architecture contributes more improvements in clock delay, wire length, and power consumption than those of Manhattan architecture. This work proposed an X-architecture zero skew clock tree construction with buffer insertion and sizing. A pattern matching...
Signal propagation delay on a multi-source multi-sink bidirectional bus has a dominant effect on high-performance chips. This work presents a novel greedy algorithm that minimizes the critical propagation delay of an RLC-based bus. Based on the topology of a multi-source multi-sink bus and the RLC delay model, the proposed algorithm inserts signal repeaters into the critical path of the RLC-based...
The antenna effect is a phenomenon in the plasma-based nanometer processes that many charges are accumulated on metal wires which cause the degradation of gate-oxide. It also influences the chip reliability and manufacturing yield. Different with other methods based on Manhattan-architecture for the antenna avoidance, we propose the algorithm that combines jumper insertion and layer assignment (JILA)...
In this paper, we propose an X-architecture routing algorithm for a clock network. With the definition of 16-pattern X-routing for a pair of points, our algorithm applies these patterns to simplify the selection of merging segments whereas using the DME approach and constructs an X-clock tree with zero skew. An X-flip is employed to shorten the wire length of each pair of points as possible for minimal...
As the advanced process and shrinking feature size integrate more and more functions on one chip, accompaniments are problems of lithography and material defects affecting the yield and quality of the chip beyond nanometer process. Via defects and congested wires are not beneficial for manufacturing in clock network and they should be avoided in the design. In this paper, we refine these defects by...
In this paper, the authors propose a greedy algorithm to minimize the maximal propagation delay for giving the topology of a multi-source multi-sink bus with RLC delay model. The algorithm minimizes the maximal delay by inserting signal repeaters into the critical path and adjusts their sizes, and repeats the above procedure until no any improvement in delay reduction. Experimental results exhibit...
In this paper, the authors propose a new numerical method of tapping point search based on uniformly distributed RLC wire model. A tapping point for two subtrees based on the numerical analysis of the model is always determined for exact zero skew. With the bottom-up recursion, the characteristic of zero skew upward propagation for two hierarchical subtrees is proved for a multi-level clock tree....
The paper first analyzes the crosstalk interaction for two RLC-based clock routings with considering both coupling capacitance and mutual inductance. Running results based on 0.13mum process show our observations: (a) the difference between clock delays in different frequencies is very small because the damped factor is always larger than 1 for a long-wire clock routing; (b) the crosstalk interaction...
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