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We report low Vt (Vt,Lg=1μm=±0.26V) high performance CMOS devices with ultra-scaled Tinv down to Tinv~8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS Tinv (2) 220mV lower long channel...
In this paper, we have done a comprehensive study of the junction anneal strategy (by spike and/or laser) for advanced technology nodes with Hk/MG and high-k capping film to control the eWF. It has been shown that a low long channel Vth is easily achievable with anneal sequence optimization. In particular with the help of laser which creates more dipoles for NMOS case with La-based capping. But also...
In this paper, we report on the integration of laser-annealed junctions into a state-of-the-art high-k/metal gate process flow. After implant optimization, we achieve excellent Lg scaling of 15/30 nm over a spike reference, for nMOS and pMOS respectively, without any performance loss. This enables to fabricate transistors with Lgmin meeting the 32 nm node requirement. In addition, we highlight the...
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by...
The Ni-silicide phase formation in FUSI gates was investigated comparing soak and spike anneals for the first RTP step. From both physical analysis on blanket wafers and electrical measurements on nMOS FUSI/HfSiON device it is found that the RTP1 temperature process window (PW) to obtain NiSi or Ni3Si2 at the FUSI/dielectric interface is significantly widened for spike anneals (30degC < PW <...
We report record unloaded ring oscillator delay (17ps at VDD = 1.1V and 20pA/mum Ioff) using low power CMOS transistors with Ni-based fully silicided (FUSI) gates on HfSiON. This result comes from two key advancements over our previous report presented in A. Lauwers et al. (2005). First, we have improved the (unstrained) devices Idsat to be 560/245muA/mum for nMOS/pMOS at an Ioff = 20pA/mum and V...
This work presents the first comprehensive evaluation of the manufacturability and reliability of dual WF phase controlled Ni-FUSI/HfSiON CMOS (NMOS: NiSi; PMOS: Ni2Si and Ni31 Si12 evaluated) for the 45 nm node. RTP1 and poly/spacer height were identified as the most critical process control parameters in our flow. We demonstrate that a novel sacrificial SiGe cap addition to the flow (improved poly-Si/spacer...
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