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A detailed statistical characterization and modeling of drain current local and global variability in 14nm Si bulk FinFET devices is performed. To this end, an analytical mismatch model covering weak to strong inversion region is used to extract the main matching parameters. Our results show that, despite their very aggressive dimensions in terms of Fin width and height, such devices exhibit excellent...
In this paper, we illustrate how high resolution two-dimensional (2D) carrier maps obtained from scalpel scanning spreading resistance microscopy (s-SSRM) can be applied to calibrate a technology computer aided design (TCAD) simulator in order to predict and understand the performance of sub-10nm WFIN FinFETs. In the proposed approach, process simulations are calibrated such that the resulting simulated...
We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors. Among the considered technologies, nanoscaled SiGe channel devices show smallest time-dependent variability. Furthermore,...
This work assesses the impact of process variability such as device mismatch of two in-house FinFET and a planar technology on key figures of merit (SNM and WTP) of SRAMs - for the first time not only at cell but also at product level. We show that the statistical cell response in the very end of the tails is the key metric that determines SRAM yield, which is quite different between the SRAM cell...
The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins...
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