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This paper presents an experimental analysis of the influence of the silicon thickness (tsi)and the channel length (L) on the threshold voltage (Vt), subthreshold swing (SS), drain induced barrier lowering (DIBL), gate induced drain leakage (GIDL) and the ON-state over OFF-state current ratio (ION/IOFF))on Ultra Thin Buried Oxide (UTBOX) and Ultra Thin Body and Buried oxide (UTBB) SOI nMOSFET devices...
This paper reports for the first time the study of radiation effects on triple gate SOI tunnel FETs. In this work, devices with 1 μm width and three different channel lengths were exposed to a 600 keV proton radiation source and their current-voltage behavior was analyzed after 1 Mrad(Si) of accumulated total dose, comparing the results obtained before and after irradiation. It was possible to notice...
Future technologies put stringent demands on materials, process modules and device architectures. Design considerations favor the future use of vertical devices like tunnelFETs and nanowires. Heterogenous integration of Ge and III-V technologies on a silicon platform enables to fabricate System-on-Chip applications, while increased functionality is achieved by 3D integration. Attention is also given...
This paper gives a proper characterization of n-channel UTBOX nMOSFETs in linear operation in term of static performances and low frequency noise behavior. At first, the main electrical parameters are extracted, in particular, the threshold voltage, the mobility and the access resistances. Then, the approach of low frequency noise study is presented as a non-destructive diagnostic tool to identify...
This paper brings a comparison of the traps identified in triple-gate FinFETS and Gate-All-Around (GAA) nanowire (NW) MOSFETs built with the same technological process. Traps have been identified using low frequency noise (LFN) spectroscopy, giving information on which process steps may be improved in order to build better devices.
The assessment of deep traps in In0.3Ga0.7As nFinFETs by Generation-Recombination (GR) noise spectroscopy is described in this paper. The gate voltage dependence of the corner frequency is studied for several devices with different gate lengths. Both gate-voltage-independent and gate-voltage-dependent corner frequencies are found. It is shown that the noise type turns from GR to Random Telegraph Signal...
Low frequency noise is investigated in n-type UTBOX transistors presenting different channel orientations (standard μ100ξ and rotated μ110ξ). It was observed that decreasing temperature reduces the 1/f noise level particularly for a short rotated device. However, unexpected variation of the flicker noise in strong inversion was observed for the long rotated channel. Furthermore, evolution of generation-recombination...
The low-frequency noise behavior in linear operation of input-output (I/O) pMOSFETs for Dynamic Random Access Memory (DRAM) applications is studied for different process conditions: the 5 nm SiO2/2 nm HfO2/TiN stack is compared with a wafer subjected to a post-deposition SF6 plasma treatment and with a split where TiN is replaced by a TaN metal gate. It is shown that while the variability in the noise...
Unusual peaks in the transconductance gm(VGS) characteristics of n-channel UTBOX devices have been evidenced at 10 K and 77 K operation for an applied front gate voltage around 1.1 V while the back gate is grounded. The origin of this behavior was also addressed using additional low frequency noise (LFN) measurements. It is believed that the unusual peak may be related to a tunneling effect through...
In this work, DC and low frequency noise have been investigated in Gate-All-Around Nanowire MOSFETs at very low temperatures. Static characteristics at 4.2 K exhibit step-like effects that can be associated to energy subbands scattering. The mobility and subthreshold swing are also investigated. Finally the low frequency noise spectroscopy (from 10 K to 70 K) leads to the identification of silicon...
In this work, the influence of the temperature and the different equivalent oxide thickness (EOT) of In0.53Ga0.47As nTFETs fabricated with gas phase Zn diffusion is analyzed. The different devices have in their gates stacks 3 nm of HfO2 (with an EOT of 1 nm) or 2 nm of HfO2 (with an EOT of 0.8 nm). The use of an EOT of 0.8 nm increases the band-to-band tunneling generation and also improves the subthreshold...
This paper studies for the first time the low temperature characteristics of strained SOI FinFETs submitted to proton irradiation. Both types of transistors, nMOS and pMOS, were analyzed from room temperature down to 100K, focusing on the threshold voltage (VTH), subthreshold swing (SS), the Early voltage VEA and the intrinsic gain voltage (AV). The effects of strain techniques are also studied. The...
The experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to...
Continued scaling of DRAM technologies has required a limitation of the power dissipation from the peripheral region of the chip, while downscaling transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-κ metal-gate (HKMG) stacks into periphery and high-voltage DRAM I/O devices. Being the peripheral...
This paper gives a proper characterization of n-channel UTBOX nMOSFETs in linear operation in term of static performances and low frequency noise behavior. At first, the main electrical parameters are extracted, in particular, the threshold voltage, the mobility and the access resistances. Then, the approach of low frequency noise study is presented as a non-destructive diagnostic tool to identify...
This work reports for the first time on the experimental study of the intrinsic voltage gain of InGaAs nTFET. The influence of Indium/Gallium composition and Zn diffusion temperature is analyzed. For a higher Indium amount (In0.7Ga0.3As compared to In0.53Ga0.47As) the band to band tunneling (BTBT) is improved due to bandgap narrowing. A higher Zn diffusion temperature gives rise to a higher source...
This paper studies the carrier mobility of triple gate SOI nFinFETs, fabricated on standard and rotated substrates, varying the fin width. The effective mobility results were extracted using the Split CV method, where FinFETs fabricated with rotated substrate show a higher maximum mobility than devices fabricated with a standard substrate. The effects of biaxial strain were also analyzed for the maximum...
Random Telegraph Signal noise has been extensively studied for more than 30 years and gained high interest in recent years due to its importance for scaled down technologies. This review will demonstrate the power of RTS for single defect characterization. Present understanding of the device physics and evolutions in RTS characterization are highlighted. Special attention is given to RTS in memory...
We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower IOFF values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (WNW≤25nm, HNW∼22nm), with increased doping enabling ION improvement without IOFF penalty for WNW ≤10nm. These...
For the first time, an RTN based defect tracking technique has been developed that can monitor the defect movement and filament alteration in RRAM devices. Critical filament region has been identified during switching operation at various conditions and new endurance failure mechanism is revealed. This technique provides a useful tool for RRAM technology development.
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