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We designed an addressable transistors array to analyse local variability at the wafer scale. On FDSOI substrates, we measure no impact of the silicon thickness variations on short channel transistors, and demonstrate that the impact on large area transistors is no more visible when the Tsi is well controlled.
For the first time, a huge drain current fluctuations degradation is shown on heavily pocket-implanted above-micrometer devices. This degradation, which is a serious concern for analog design, is attributed to the high potential barriers that stand at end sides of long devices and mainly control the device electrostatics. Because the barriers height is modulated by the gate voltage, it is demonstrated...
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