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A low latency high throughput Dynamic Virtual Output Queues Router for On-Chip interconnect networks is proposed in this paper, which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output queues scheme. Compared to wormhole router and virtual channel router, Simulation results show that network throughput on a 4×4 mesh increases by up to 46.9%...
Non-uniform distribution of memory accesses across cache sets has been recognized as one of the sources of inefficiency of cache architecture on single-core platform. Several schemes target the problem for performance boost. As chip multiprocessors (CMPs) pick up steam as the mainstream processor design choice, how non-uniform distribution of memory accesses across cache sets affects the cache management...
With the number of processor cores increasing in chip multi-processors (CMPs) and global wire delays increasing, networks on chip have been gaining wide acceptance for on-chip inter-core communication. This paper introduces a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output address...
On chip multiprocessors (CMPs) platforms, multiple co-scheduled applications can severely degrade performance and quality of service (QoS) when they contend for last-level cache (LLC) resources. Whether an application will impose destructive interference on co-scheduled applications is largely dependent on its own inherent cache access behavior characteristics. In this work, we first present case...
In this paper, a 2mm-long linear on-chip dipole antenna pair on Si substrate is analyzed and simulated to investigate the transmission characteristics using Ansoft's HFSS. By inserting a 0.35mm thick diamond layer between substrate and heat sink, the obtained transmission gain of antenna pair with 1mm separation on 10 Ohm-cm Si substrate increases by 9dB at 20GHz. The effect of the dielectric materials,...
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