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Desynchronized circuits outperform the synchronous counterparts in power, performance, robustness according to many studies, and delay elements are important components by mimicking the critical path delay of two arbitrary correlated latches to act as completion detection logic. In classical design flow, the critical path delay is derived through static timing analysis (STA); however, this approach...
This paper presents a floating-point fused multiply-add (FMA) unit with low-cost and low power techniques. To improve the performance, two single-precision operations can be performed concurrently with one double-precision datapath, which is very useful in multimedia and even scientific applications. Moreover, to reduce the additional area costs for supporting two single-precision operations in parallel,...
For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (random access memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This paper presents some novel techniques to improve at-speed testing coverage with low cost. These methods are major concern about preventing X states propagation, which include avoiding capturing...
Test power is becoming a very important design consideration nowadays. In this paper, we apply power gating technique into scan-based designs for the first time to eliminate both dynamic and static power of idle logic during shift process. Different from any traditional coarse-grain or fine-grain power gating scheme, our proposal does not need to change design infrastructure and only tailors existing...
This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (scalable mesh of crossbar) on-chip network and targets high-end applications. Advanced techniques are adopted to achieve the scalable, low-power and low-cost scan architecture at the challenge of limited I/O resources and large scale of transistors...
Scan-based test methodology is used to resolve the sequential-test problem but suffers from high power dissipation. In this paper, we propose a scheme to prevent transitions of scan chain from reflecting into the circuit line. It not only can save 23% power consumption without performance loss, but also can be easily implemented with popular industrial design tools.
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