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A new cell structure of NAND memory devices, which employs an additional nitride layer between the top of a floating gate (FG) and inter-poly dielectrics (IPD), is devised to lesson a high electric field on the FG top edges during program. The cell structure is proved to be promising in sub-20 nm NAND generation in terms of larger program window, better endurance, and more robust data retention, which...
This paper presents a capacitor-less 1T DRAM cell transistor with high scalability and long retention time. It adopts gate to source/drain non-overlap structure to suppress junction leakage, which results in 80 ms retention time at 85degC with gate length of 55 nm. Compared to the previous reports, proposed cell transistor shows twice longer retention time even though the gate length shrinks to the...
Ultra Thin Body Si-On-ONO (UTB SOONO) transistors with ultra thin spacer are successfully demonstrated and evaluated. They have shown increased driving current more than 30% compared with conventional UTB SOONO transistors with thick spacer due to reduced source/drain resistance without short channel effect degradation by using thin spacer. In this paper, it is shown that thin spacer technology is...
As DRAM cell pitch size scales, the DRAM cells have required characteristics of high performance transistors. In this paper, we proposed and successfully demonstrated high performance silicon-on-ONO (SOONO) cell array transistors (SCATs) for 512Mb DRAM cell array application. They have advantages of SOI substrate and 3-D hi-gate as well as process simplicity. From those advantages, they have low Ioff...
In this study, we compared sensing margin according to the back gate bias and body doping concentration. We achieved large sensing margin of 62 uA/um at LG = 87 run and demonstrated sensing margin of 45 uA/um with LG = 47 nm that is the smallest device ever reported for the floating body RAM. For the scaling down to the sub 50 nm gate length, we should reduce the body thickness for the SCE with optimum...
We completed the demonstration of three key functions of SOONO devices by demonstrating the DRAM characteristics of FD and PD SOONO devices successfully, together with the previously reported logic transistor and flash memory characteristics. Floating body SOONO DRAM cells implemented on electrically thin buried insulator shows the large sensing margins more than 5??A in FD device with long data retention...
In this article, we report improved results of 4-bit double SONOS memories (DSMs) with 4-storage nodes through the optimization of ONO layer thicknesses for front and back sides. They show more balanced characteristics between the front and back channels, higher VTH shifts above 2.4V, larger read margins above 1.6V, better endurance, and longer retention time than our previous results. In addition,...
In this article, we proposed and successfully demonstrated 25 nm TiN metal gate nanorod transistors with laterally and vertically scaled actives without process burdens. They showed the excellent short channel effect immunity and high current drivability DIBLs are below 40 mV/V and subthreshold swings are nearly ideal values showing no temperature dependency. The driving currents of 1.4 mA/mum for...
As planar MOSFETs are scaled down, it is more and more difficult to achieve the scaled transistors with high performance. One of the key issues must be large source/drain (S/D) resistance as well as short channel effects (SCEs) (Ghani et al., 2001). These are in trade-off relation because shallow junction for reducing SCEs causes the increase of S/D resistance. One of the solutions to solve both problems...
We proposed and successfully demonstrate multi-functional Si-on-ONO (SOONO) MOSFETs. As a high performance transistor and embedded 2-bit flash memory, they show the reasonable characteristics. SOONO MOSFETs act as ultra thin body transistor with self-limited shallow junction, resulting in good SCE immunity and high driving currents, 737muA/mum for nMOS and 330muA/mum for pMOS at |VGS| = |VDS| = 1...
For the first time, titanium-nitride (TiN) single metal gate and high-k hafnium-silicate (HfSiOx) gate dielectric have been successfully integrated in 55nm McFET SRAM cell. The use of HfSiOx gate dielectric, not only reduces gate leakage current but also improves ION/IOFF ratio of PFET to 108. Using local fin implantation (LFI) scheme, junction capacitance is reduced by 13% and junction breakdown...
We proposed a 4-bit double SONOS memory with two ONO layers, 4 storage nodes, for ultimate multi-bit operation and firstly demonstrate 4-bit operation using the physically separated 4 storage nodes. By using CHEI/HHI program/erase, each node was easily programmed and erased without any detrimental interference among the nodes. In the gate length of 120nm, the read/write margins of ~0.8V for front...
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