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In this work, we demonstrate a 6.9 sq. /spl mu/m embedded SRAM cell in a 0.25 /spl mu/m physical design-rule salicide high-performance CMOS technology. The scalability of this salicide-CMOS embedded-SRAM technology is demonstrated by functionality of the same SRAM cell implemented in 0.35 /spl mu/m and 0.25 /spl mu/m design rules. To our knowledge this is the smallest reported SRAM cell in a salicide-only...
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