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In this Letter a new compensation strategy for a class of three-stage operational transconductance amplifiers is proposed. The proposed approach reduces the original third-order transfer function of the loop gain to that of a pure two-pole amplifier thus allowing the designer to use well-known and consolidated design rules. The approach, suitable for high-speed switched-capacitor circuits, is validated...
In this paper, the effect of intradie process variations on the delay of tapered buffers designed in static CMOS logic style is analyzed in depth. An analytical delay model accounting for the dependency of variations on transistor sizing, load and input capacitance requirement is derived for the single stage. Then, this model is extended to the case of N-stage tapered buffers. The closed-form delay...
In this paper, the effect of process variations on the delay of CMOS static logic circuits is discussed versus fan-in. In particular, the effect of process variations in stacked transistors (which determine the fan-in) is analytically evaluated. From circuit analysis, a simple analytical model is derived that expresses the delay variation as a function of the number of stacked transistors and transistor...
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