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This paper presents both experimental and TCAD simulation results on a planar tunneling field-effect transistor (TFET) using compressively strained Si0.45Ge0.55 on Si. Introducing a counter doped pocket at the source tunnel junction in combination with a selective and self-adjusted silicidation to enlarge the tunneling area enables line tunneling aligned with the gate electric field which results...
Complementary MOSFET and Tunnel-FET inverters based on tri-gated strained Si nanowire arrays are demonstrated. The voltage transfer characteristics as well as the inverter supply currents of both inverter types are analyzed and compared. A degradation of the inverter output voltage is observed due to the ambipolar TFET characteristics. Emulated TFET inverters based on the measured transfer characteristics...
This paper presents experimental results on tunneling field-effect transistors (TFETs) based on SiGe on SOI nanowire arrays. A SiGe-Si heterostructure TFET with a vertical tunneling junction consisting of an in situ doped SiGe source and a Si channel is demonstrated. The device shows switching behavior over a drain current range of up to 8 orders of magnitude with a minimum slope of 90 mV/dec. A larger...
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