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The chemical reactions at the higher-k LaLuO3/Ti1NX/poly-Si gate stack interfaces are studied after high temperature treatment. A Ti-rich TiN metal layer degrades the gate stack performance after high temperature annealing. The gate stack containing TiN/LaLuO3 with a near stoichiometric TiN layer is stable during 1000 °C, 5s anneals. Both electrical and structural characterization methods are employed...
We report on the fabrication and electrical characterization of Ω-gated nanowire (NW) array pFETs on SOI. Devices with gate lengths of L = 400nm and L = 2 μm and 〈110〉 - and 〈100〉 - channel orientations were fabricated using a top-down approach. Each device consists of up to 1500 NWs with a crosssection of 20 × 20 nm2. The devices feature excellent electrical characteristics with high on-currents,...
High performance Schottky barrier MOSFETs require metallic source/drain contacts with very low Schottky barrier heights. This investigation focuses on barrier lowering via silicidation induced dopant segregation at the NiSi/Si interface with particular emphasis on the influence of dopant activation prior to Ni-silicidation. Diodes with activated dopants reveal significantly lower Schottky barrier...
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