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The chemical reactions at the higher-k LaLuO3/Ti1NX/poly-Si gate stack interfaces are studied after high temperature treatment. A Ti-rich TiN metal layer degrades the gate stack performance after high temperature annealing. The gate stack containing TiN/LaLuO3 with a near stoichiometric TiN layer is stable during 1000 °C, 5s anneals. Both electrical and structural characterization methods are employed...
The integration of lanthanum lutetium oxide (LaLuO3) with a n value of 30 is, for the first time, demonstrated on strained and unstrained SOI n/p-MOSFETs as a gate dielectric with a full replacement gate process. The LaLuO3/Si interface showed a very thin silicate/SiO2 interlayer with a Dit level of 4.5 × 1011 (eV · cm2)-1. Fully depleted n/p-MOSFETs with LaLuO3/TiN gate stacks indicated very good...
P-MOSFETs with HfO2 gate dielectric and TiN metal gate were fabricated on compressively strained SiGe layers with a Ge content of 50 at.% and electrically characterized. The devices showed good output and transfer characteristics. The hole mobility, extracted by a split C-V technique, presents a value of ~200 cm2/V·s in the strong inversion regime.
Integration of lanthanum lutetium oxide (LaLuO3) with a κ value of 30 is demonstrated on high mobility biaxially tensile strained Si (sSi) and compressively strained SiGe for fully depleted n/p-MOSFETs as a gate dielectric. N-MOSFETs on sSi fabricated with a full replacement gate process indicated very good electrical performance with steep subthreshold slopes of ~72 mV/dec and Ion/Ioff ratios up...
We report on the fabrication and electrical characterization of Ω-gated nanowire (NW) array pFETs on SOI. Devices with gate lengths of L = 400nm and L = 2 μm and 〈110〉 - and 〈100〉 - channel orientations were fabricated using a top-down approach. Each device consists of up to 1500 NWs with a crosssection of 20 × 20 nm2. The devices feature excellent electrical characteristics with high on-currents,...
Ultra thin Ni-silicides were formed on silicon-on-insulator (SOI) and biaxially tensile strained Si-on-insulator (SSOI) substrates. Epitaxial NiSi2 layers were formed with a 3 nm Ni layer at T > 400°C, while a polycrystalline NiSi layer was with a 5 nm thick Ni layer. The NiSi2 layer quality advances with increasing temperature. A very thin Pt interlayer, to incorporate Pt into NiSi, forming Ni...
Recent experimental results on Si nanowire MOSFETs are presented. The devices were fabricated in a top-down approach on unstrained and biaxial strained SOI substrates exhibiting good I-V characteristics with Ion/Ioff-ratios of 107 and off-currents as low as 10-13 A. Subthreshold slopes of about 70 mV/dec for SOI n- and p-FETs and 65 mV/dec for strained SOI n-FETs were obtained. The on-current and...
In this paper, we present fully-depleted Schottky barrier MOSFETs with dopant-segregated NiSi source and drain junctions. Schottky barrier MOSFETs with a channel length of 80 nm show high on-currents of 900 muA/mum for n-type devices with As segregation and 427 muA/mum for p-type devices with B segregation, respectively. A detailed high-frequency characterization proves the high performance of the...
This paper presents fully-depleted short-channel Schottky barrier (SB) MOSFETs with silicidation induced dopant segregation of B at a low temperature of 450degC. The integration of nickel silicide combined with either As or B segregation significantly improves the switching performance of dopant-free SB-MOSFETs. The implantation dose dependence of the device characteristics is studied on long channel...
High performance Schottky barrier MOSFETs require metallic source/drain contacts with very low Schottky barrier heights. This investigation focuses on barrier lowering via silicidation induced dopant segregation at the NiSi/Si interface with particular emphasis on the influence of dopant activation prior to Ni-silicidation. Diodes with activated dopants reveal significantly lower Schottky barrier...
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