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As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry. But due to the circuit complexity, the high pin counts and ever increasing operating frequencies, System-on -Chip (SoC) devices drive the most challenging requirements for failure localization and mechanism analysis. PEM (Photon Emission Microscopy)...
In this study, we introduce a far field-aware system on a chip (SOC) design for sound source location, which is implemented with 0.18-μm CMOS process. The adopted method for the proposed system is based on average magnitude difference function (AMDF). In order to effectively detect the acoustical source in actual environment, we integrate this system with voice active detection (VAD), which can actively...
We present a novel testing scheme for TSVs in a 3D IC by performing on-chip TSV monitoring before bonding, using a sense amplification technique that is commonly seen on a DRAM. By virtue of the inherent capacitive characteristics, we can detect the faulty TSVs with little area overhead for the circuit under test.
As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry due to the rapid increasing rate of radiation-induced soft errors while the SoC fabrication enters the very deep submicron technology. Therefore, the SoC dependability becomes a critical issue in safety-critical applications. Validating such...
Intelligent systems, such as intelligent car driving system or intelligent robot, require a stringent reliability while the systems are in operation. As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry while the SoC fabrication enters the very deep submicron technology. In this study, we present...
As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry while the SoC fabrication enters the very deep submicron technology. In this study, we present a new approach of system-bus fault injection in SystemC design platform, which can be used to assist us in performing the FMEA procedure during the...
Embedded systems, and also the embedded microprocessors, have encountered the reliability challenge because the occurring probability of soft errors has a rising trend. When they are applied to safety-critical applications, designs with the fault tolerant consideration are required. For the complicated embedded systems or IP-based system-on-chip (SoC), it is unpractical and not cost-effective to protect...
In this paper we present the architecture for virtual self-timed blocks. Being globally asynchronous locally synchronous (GALS) and lazy reactive processing units, such blocks target multi-processing on-chip systems where power consumption is an important factor. The architecture provides a hardware foundation which transparently supports the systematic organization of application-level activities...
As system-on-chip (SoC) becomes more and more complicated, and contains a large number of transistors, the SoC could encounter the reliability problem due to the increased likelihood of faults or radiation-induced soft errors when the chip fabrication enters the deep submicron technology. Thus, it is essential to employ the fault-tolerant techniques in the design of SoC to guarantee a high operational...
Intellectual properties (IP cores) are widely used as pre-designed and reusable units in various system-on-chip (SOC) designs, but their integration has presented difficulties for system designers. In this paper, we propose an approach to better reuse IP cores while maintain energy efficiency for SOC systems. Here we employ a so called self-timed event processor (STEP) to make each IP core into a...
An SoC for high-speed read and write functions is designed for multi-formats of 7/spl times/BD/16/spl times/DVD/56/spl times/CD at channel bit rates of 462/418/242Mbit/s. The data is detected by a PRML detector. The ECC CODEC for all formats is integrated as a single RS-CODEC. The SoC is implemented as a 30mm/sup 2/ die in a 0.18 /spl mu/m 1P6M CMOS process and consumes 1.0/0.9/0.7W in 7/spl times/BD/16/spl...
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