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The increasing application demands put great pressure on high performance processor design. This paper presents a multi-core System-on-Chip architecture for high performance computing. It is composed of a sparcv8-compliant LEON3 host processor and a data parallel coprocessor based on transport triggered architecture, all of which are tied with a 32-bit AMBA AHB bus. The LEON3 processor performs control...
Multi-core processor has become the mainstream processor nowadays. Data communication between different cores becomes a main problem especially when many cores need to get data from one core. Traditional Client/Server mode communication pattern tends to cause the server node to be the bottleneck and only uses the transfer path between the client and server nodes. A P2P communication model is proposed...
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