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In this paper we propose a strategy for better exploiting Multi-Processor Systems-on-Chip resources utilization by means of using a control-loop feedback mechanism. We apply the proposed techniques in a purely distributed memory MPSoC architecture that is composed of a frequency scaling module responsible for tuning the frequency of processors at run-time. Results show very promising in terms of adaptation...
We will present a survey of trends in the semiconductor industry for programmable hardware. The main objective of this paper is educational and the focus is FPGAs and its related or vs technologies which have emerged mostly in the second half of the last decade. We will try to analyze what were the prominent reasons for emerging of these technologies. What are the advantages and drawbacks of them,...
In this paper, we present a flexible and distributed homogeneous Software Defined Radio (SDR) platform. This platform is an array of processing elements, called Smart ModEm Processors (SMEP), interconnected by a Network-on-Chip. Implemented in ST65nm, each processing element performs 3.2 GMAC/s with 77 GBits/s internal bandwidth while dissipating 110mW. Each SMEP unit contains a MIPS processor for...
In this paper we propose an adaptive technique to reduce power consumption of Multiprocessor Systems-on-Chip. The method, based on Game Theory, optimizes the frequencies of local processors while fulfilling applicative real-time constraints. Contrary to other approaches, our solution is compatible with reconfigurable Systems-on-Chip. The obtained power consumption gains on a telecommunication test-case...
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