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For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and drive current over our best poly-gate 45 nm-node nMOSFET with SMT and tensile liner stressors. In addition, eSi:C showed better scalability than SMT plus tensile liner stressors from 380 nm to 190 nm poly-pitches.
For nFET, mechanism of stress memorization technique (SMT) has been investigated. It showed, for the first time, that SMT effect on nFET improvement is not only from poly gate, but also from Si at extension area. For pFET, a novel low cost technique to improve device performance by enhanced stress proximity technique (eSPT) with Recessed SD (ReSD) has been demonstrated for the first time. pFET performance...
The device characteristics and manufacturability of ultra-thin oxynitride have been systemically studied in this paper for CMOS applications. We have found that the transistor with plasma oxynitride gate dielectrics gives better pFET performance in terms of drive current, mobility, threshold voltage and leakage current as compared to the one with thermal oxynitride. For nFET, the performance for transistors...
As CMOS devices further scale down, the variation of electrical parametric becomes significant and is critical for VLSI design. However, the difficulty in device statistical modeling also increases. The parasitics and second-order effect are not negligible, and the impact of process variations on device parametrics are usually correlated, which complicates the extraction of industry standard models...
This paper presents for the first time (110) PMOS characteristics without Rext degradation, allowing investigation of fundamental mobility and demonstration of drive current Ion in excess of 1mA/mum at Ioff =100 nA/μm.
History effects in 65-nm partially-depleted silicon-on-insulator CMOS technology are systematically measured and characterized. The impact of various process adjustments on these effects is analyzed, and an optimization strategy is presented. Hardware data show >9% history effect changes is controllable with no loss of performance (e.g. speed and leakage), offering more flexibility in SOI circuit...
We report, for the first time, a detailed study of intra-die variation (IDV) of CMOS inverter delay for the 65nm technology, driven by mm-scale variations of rapid thermal annealing (RTA). We find that variation in VT and REXT accounts for most of the IDV in delay and leakage and is modulated by lamp RTA ramp rate. We show a good correlation of inverter delay to mm-scale variation in the predicted...
Floating-gate MOS memories based on single electron effect are very attractive, because of the potential quantized threshold voltage shift, quantized charging voltage to create the shift, small device size and fast charging time. However, to relax the challenges in fabricating such devices, previous single-electron MOS memories (SEMMs) had to have nonconventional structures (e.g. a polysilicon channel...
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