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A scaling feasibility for the process integration of the Ti/HfOx, resistance memory with pillar structure is studied in this letter. An empirical model is successfully developed to correlate the forming voltage of devices to their cell sizes. The abnormal increase in the breakdown voltage and the absence of the resistance switching characteristic for the scaled devices (<; 150 nm) are observed...
In this work, the nanoscale Ti/HfO2 based resistive memory with pillar structure was fabricated. The architecture of the pillar device shows the advantages of reduced parasitic capacitance effect and simple process flow. The effects of the passivated layer on the nanoscale RRAM are also studied. Reduction of the interaction between the memory device and the encapsulating layer plays an important role...
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