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Single-event upset (SEU) responses of advanced dual- and triple-well planar technologies show significant differences in SEU cross-section for memory cells. The presence of the third well alters the charge-collection mechanism as well as increases the probability of charge sharing, affecting the SEU responses of memory cells. However, at the 16-nm FinFET technology node, heavy-ion experiments show...
28-Nm planar, 20-nm planar, and 16-nm FinFET technology combinational and flip-flop circuits are investigated using different LET particles. An analytical model is developed to study the ratio of logic to flip-flop (FF) single-event (SE) cross-section as a function of LET particles. Results indicate that high-LET particles have a much stronger impact on the logic single-event (SE) cross-section as...
With fabrication processes migrating from planar devices to FinFETs, the differences in physical structure necessitate evaluating the SEU mechanisms of FinFET-based circuits. Since FinFET-based bi-stable circuits have shown better stability at low supply voltages and hence improved power dissipation, it is also necessary to assess the SEU performance over a range of voltages. In this work, the SEU...
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