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Mission profiles for semiconductor applications are getting more and more challenging regarding electrical and thermo-mechanical robustness of metallization stacks. Effects, especially in thick metals, were investigated over the last years to find solutions for an improvement regarding both potential stressors. Some elements of a metallization were designed, investigated and simulated [1, 2, 3, 4...
This paper presents a new SOI BCD technology at the 0.18μm node to fulfill the requirements for smart power IC technology targeted for automotive application. Built on a 1.8V and 5.0V CMOS core, there are 40V and 60V rated N/Pch MOS, with 25mΩ.mm2 RonA/57V BVdss having been achieved for the 40V NMOS with excellent process stability. Depletion NMOS, LV&HV diodes, 5V zener diode, high gain BJT,...
For mixed signal applications it is necessary to have metallization which are able to carry high currents. Also the on chip integration leads to special requirements on the metallization concerning their robustness. A common method for the determination of interconnect lifetime is described in JP001A and based on Black's law and the measurement of time to failure, medium stress current density and...
A framework to generate predictive simulations is proposed to investigate the influence of system's mass on manual wheelchair locomotion. The approach is based on a model of wheelchair propulsion dynamics and an optimal control formulation. In this study, predictive simulations of steady-state wheelchair locomotion are generated for different combinations of model mass and uphill slope inclination...
Highly robust metallizations in ICs for high temperature and high current applications are needed. Special thick metal layers often known as “power metals” are added to achieve a higher current capability. But these metallizations suffer from reliability limitations as well. Therefore a new design for “power metals” was created for a 0.35µm aluminium CMOS process. The reliability of a new power metal...
For high temperature automotive applications a 0.35 µm aluminium CMOS is one of the common technology processes. In this process Ti/Al/Ti/TiN stacks are used as metallization. These aluminium stacks form TiAl3 layers during the following annealing step. The thermal-electrical and thermo-mechanical properties of this metallization is different from titanium or aluminium. Hence the forming TiAl3 layer...
The article at hand presents the results of thermoelectrical simulations of migration effects in integrated interconnect systems in comparison to measurement data. The simulation concept will be described and the output values as mass flux divergence and time-to-failure (TTF) will be discussed. Based on the example of via chain structures, different geometry factors have been investigated with respect...
Lithium niobate (LiNbO3) is a frequently used material for nonlinear optics, due to its large nonlinear coefficent and high transparency over a large wavelength range. Domain engineering is needed to achieve quasi-phase matching which is necessary to address a wide wavelength range.[1] The domain engineered bulk crystals certainly yield the highest effective nonlinear coefficients, but the design...
This paper aims at demonstrating the capabilities of predictive, computational simulations of gait in clinical applications. In particular, the gait with bilateral and unilateral Ankle Foot-Orthoses (AFO's) is investigated. The problem is formulated in an optimal control framework where optimal motion and neural excitations to the muscles are computed solely on the basis of an assumed optimality criterion...
This paper investigates the use of a metal control gate for sub 30 nm NAND flash memory. It is shown that polysilicon control gates are not effective at reduced feature sizes due to poor electrical conductivity. As the physical dimensions scale and the doping level of the polysilicon decreases, especially at the beginning of polysilicon deposition, the control gate plugs become electrically non-functional...
This article details an anomalous erase behavior in charge trapping memory devices which is visible in a characteristic erase hump in transient erase curves. For an initial period of time a Vt increase is seen when erase condition are applied to virgin cells before the expected erasing takes place for longer erase pulse duration. This is attributed to charges injected from the gate corners to the...
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