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An 2.5D IC could be composed of a number of functional dies operating in locked steps defined by a global clock signal. However, the clock network design across multiple dies may not be trivial as the die-to-die interconnects used for relaying the clock signal from a source die to the other receiver dies could be unpredictable in their delays in real silicon. In this work, we propose a characterization-and-tuning...
A clock network in a 3D-IC is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, studies have shown that small defects in a clock tree network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this paper, we present a novel test method to determine if a clock...
A faulty interposer in a 2.5-D integrated circuit often results in a hefty loss as the potentially expensive known-good-dies bonded on the interposer will have to be discarded as well. To avoid such a last-minute loss during a multichip integration process, built-in self-repair (BISR) is highly valuable. Even though there have been many BISR schemes in the literature, the proposed method offers a...
Testing the speed of po st-bond interposer wires in a 2.5-D stac ked IC is e ssential for silicon debugging, yield learning, and even for fault tolerance. In this paper, we present a novel at-speed test technique called Pulse-Vanishing test (PV-test), in which a short-duration pulse signal is applied to an interposer wire under test at the d river end. If the pulse signal can successfully propagate...
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