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This paper investigates the phase noise in LC oscillators with NMOS cross-coupled pair by means of a linear analysis. The latter includes the impact of noise sources that are often neglected, such as gate leakage shot noise, induced gate noise and all terminal access resistances noise. Despite not considering up-conversion of flicker noise, this linear analysis still provides reliable and useful results,...
This paper carries out a power-driven performance analysis on the most widely used LC oscillators' topologies, by means of the Inversion Coefficient methodology. The aim is to investigate on the best trade-off for Internet-of-Things related applications, where power consumption shall be minimized. The analysis is based on the BSIM6 model targeting a 40nm CMOS technology to investigate the trade-offs...
This paper presents the simplified charge-based EKV MOSFET model and shows that it can be used for advanced CMOS processes despite its very few parameters. The concept of inversion coefficient is then presented as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including the effect of velocity saturation. It is then used to...
In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks: a 6T SRAM, and a 4T XOR logic gate. Each XORAM cell makes a bitwise comparison between input data and stored data. The memory is organized in 18-bit words, and all the 18 XOR outputs bits must have a low...
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