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Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (Lg=40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic...
The electrostatic integrity of 7 nm-node bulk FinFETs (FF) is studied by TCAD. Lowly-doped bulk-FF have worse electrostatics than SOI- and GeOI-FF. However, by introducing a 200 meV band offset/quantum barrier (QB) under the channel or a > 1e18 doped ground-plane (GP), the electrostatics of bulk-FF match those of SOI-and GeOI-FF for the 7 nm-node. For sufficient substrate isolation, the band offset...
FinFETs are being considered as an attractive alternative to enable further CMOS Scaling. In this paper, a device scaling model for the electrostatics of bulk FinFETs is presented. Device parameters such as subthreshold slope (SS), threshold voltage (Vth), off-state current (IOFF)> drain-induced-barrier lowering (DIBL) are modeled showing good agreement with TCAD and experimental results. Besides...
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