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We propose a Digial-to-Time Converter (DTC) that is capable of providing infinite-delay-over-time for application in low-jitter digital phase locked loops. The DTC is implemented using phase interpolation of quadrature phase high-speed clock signals with weight coefficients generated by direct digital synthesis. Novelty of the architecture lies in using (i) a slow-settling current steering DAC that...
In most phase locked loops, an obvious trade-off exists between settling time, output jitter and power consumption. However, dependence of jitter on settling time is commonly ignored while evaluating PLL designs. In this paper, the tradeoffs between settling time and jitter is analyzed for different types of All-Digital PLLs (ADPLLs). Based on these analytical results, a Figure of Merit (FoM) for...
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