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A technological multi-chip module with a large silicon interposer has been designed, manufactured and characterized for space and airborne applications. It stands for a reconfigurable advanced calculation device, for up to 10 Gbps data rate. The electrical targets are propagation losses less than 2 dB at 5GHz for the signal path across the interposer and its bumps, signal integrity with enough eye...
A mechanical study of silicon interposer bow reduction, from wafer level manufacturing to large die stacking including analytical modeling, is presented in this paper. Indeed, understanding and reducing the warpage of a dissymmetrical substrate is fundamental for assembly yield and interconnects reliability. The target here is a bow less than 50 µm for a 650 mm2 Si-interposer.
Wafer level molding is an important process step in the chip on wafer approach and seems currently required in stacking first process flow. Thermo-mechanical properties of molding material has to be controlled to limit stress induce by CTE mismatch with silicon wafer and also to assure planarization and protection functions. 2D and 3D finite element simulations have been performed to evaluate strain...
A 6.5×6.5 mm2 compact silicon interposer encompassing 2 Tx/Rx antenna, one RF chips, TSV via-last has been designed and fabricated for 60 GHz fast data transmission applications. First characterizations are described in this paper with a focus on reliability, antenna performances and Through-Silicon-Vias (TSV) characterization. It is first shown that more than 500 thermal cycles can be achieved with...
3D integration technology opens the way of heterogeneous silicon platform, as for example, millimeter-wave functionalities could be integrated in future communication modules. Consequently, copper pillar technology realized at 1st level of interconnection between silicon top dies and silicon interposer must be evaluated in this new frequency range. In this paper, a test vehicle has been designed to...
This paper presents a reliability study on a 15×15mm2 silicon interposer packages, 5 times larger surface than usual studies on wafer level chip scale package (WLCSP). Works were conducted in the frame of silicon platform developments for heterogeneous RF 3D modules, where the interconnections number is lower than in digital applications but the silicon interposer larger than conventional WLCSP. Several...
The fabrication of a smart interposer for millimeter wave applications is described in this article. The process flow and fabrication steps are presented. A special focus is made on the electrical characterization of a specific backend routing lines and the wafer level molding material laminated on the interposer. RF properties up to 67 GHz are reported: the backend routing CPW lines exhibit an attenuation...
This paper is dedicated to the full integration of a new silicone-based material for Molding-Underfilling (MUF) on silicon interposer wafers containing Through Silicon Vias (TSVs) and top dice. The developments were carried out in the frame of “silicon package” where the silicon interposer is either reported on P-BGA or directly assembled on board. After a materials screening with regard to warpage...
This paper is dedicated to thermomechanical simulations for the development of a solder joint fatigue model for large silicon interposers. Works were conducted in the frame of silicon platform developments for heterogeneous RF or MEMS 3D modules, where the silicon interposer could be larger than conventional WLCSP. TCoB tests have been carried out on 14.6 mm×14.6 mm×0.4 mm silicon interposer with...
3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates,...
Developments in 3D integration technology reveal several basic interconnect elements, as Through Silicon Via, Redistribution Layers, Cu-Pillar and bumps to transmit signals inside 3D circuits. Impact of the interconnect elements on high speed signal integrity all along the global 3D interconnection chain requires investigation. First each element was successively characterized and an equivalent electrical...
This paper presents electrical characterization of millimeter wave interconnects on oxides to realize routing layers and through-Silicon-Vias interconnections in 3D silicon interposers. As a compromise has to be found between good RF performances and temperature compliant with 3D integration technology, a wide variety of oxide insulators are tested using coplanar waveguide transmission lines. Effects...
This paper presents electrical characterization of millimeter wave interconnects on oxides to realize routing layers and through-Silicon-Vias interconnections in 3D silicon interposers. As a compromise has to be found between good RF performances and temperature compliant with 3D integration technology, a wide variety of oxide insulators are tested using coplanar waveguide transmission lines. Effects...
This paper presents a low temperature (<350°C) hermetic solution to fully package at wafer level a RF MEMS switch connecting upwards. The switch has a piezoelectric actuation and an electrostatic hold. In this architecture, the packaging is actually part of the switch itself and shall meet many requirements: • Use of Thru-Silicon Via (TSV) for DC and RF connections with minimum via resistance •...
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