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Assertion-based verification — that is, user-specified properties combined with simulation, formal techniques, and even synthesis — is likely to be the next revolution in hardware design and verification. This chapter explores a verification break-through prompted by multi-level specification and assertion verification techniques. The emerging Accellera PSL formal property language, as well as the...
Assertion-based verification — that is, user-specified properties combined with simulation, formal techniques, and even synthesis — is likely to be the next revolution in hardware design and verification. This chapter explores a verification break-through prompted by multi-level specification and assertion verification techniques. The emerging Accellera PSL formal property language, as well as the...
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