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Speed-limiting paths are critical paths that limit the performance of one or more silicon chips. This paper present a data mining methodology for analyzing speed-limiting paths extracted from AC delay test measurements. Based on data collected on 15 packaged silicon units of a four-core microprocessor design, we show that the proposed methodology can efficiently discovered actionable, design-related...
The use of low-cost structural Fmax measurement as a replacement for in-system Fmax measurement for speed binning has been aided by the use of a data-learning approach that can be used to build a reliable single-core system Fmax predictor given structural Fmax. This paper uses industry test measurements to demonstrate how the data-learning approach can be applied to predict multi-core system Fmax,...
The detection of speed-related defects relies on fault excitation and propagation along critical speed paths in the design. Different types of structural tests detect speed paths differently. In this paper, we compare the capabilities of speed path detection using Ndetect and timing-aware transition tests on silicon. Experimental data on the latest quad-core AMD Opteron?? processor is collected. Results...
System test has been the standard measurement to evaluate performance variability of high-performance microprocessors. The question of whether or not many of the lower-cost alternative tests can be used to reduce system test has been studied for many years. This paper utilizes a data-learning approach for correlating three test datasets, structural test, ring oscillator test, and scan flush test,...
In this work, we present using random forests statistical learning to analyze post-silicon delay test data. We introduce the concept of parametric delay test as a new perspective for extracting more information from delay test. First, a methodology for outlier identification is presented to aid defect characterization of initial sample chips. Second, a methodology for production test is presented,...
In simulation-based functional verification, composing and debugging test benches can be tedious and time-consuming. A simulation-based data-mining approach (Wen et al., 2005) was proposed as an alternative for functional test pattern generation. However, the core of the approach is in solving Boolean learning, which is the problem of learning Boolean functions from bit-level simulation data. In this...
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