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We are facing the task to provide ESD protection concepts for complex system on chip (SoC) solutions including RF components, high voltage circuits and mixed signal functionality. Critical issues like protection of sensitive interfaces between supply domains, ESD master bus, system level ESD/EOS requirements and test methodology, are reviewed. Concepts are presented for a SoC and a system-in-package...
A multi-terminal TLP measurement technique is used for accessing current and voltage distributions during ESD in typical I/O cell frames in a 0.13 um CMOS technology. The procedure extends traditional I/O library testchip based ESD verification and qualification tests, allows to calibrate ESD chip-level simulation tools and to derive precise I/O library application rules.
A simulation approach is presented that allows to handle ESD simulation and analysis on a chip level complexity. In a Monte-Carlo like permutational simulation approach worst case ESD paths are identified. The simulator is embedded in an ESD analysis framework spanning from the chip protection description to an automated virtual HBM test routine with a respective fail reporting interface. The tools...
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