In this paper, an area efficient configurable design for high speed Viterbi decoder suitable for IEEE 802.11 based wireless LAN and IEEE 802.16e based WiMAX has been proposed. This design also supports the puncturing schemes defined in the above wireless standards. An area efficient VLSI design for trace back unit has been proposed in this paper. Synthesis results targeting FPGA and ASIC are included...
Financed by the National Centre for Research and Development under grant No. SP/I/1/77065/10 by the strategic scientific research and experimental development program:
SYNAT - “Interdisciplinary System for Interactive Scientific and Scientific-Technical Information”.