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This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate. Thanks to the proposed solutions, the amplifier of the loop filter is not in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed;...
A 5bit 1GS/s 0.05mm2 4× time-interleaved asynchronous digital slope ADC in 90nm CMOS for IR UWB radio is presented. New delay cells are introduced to double the speed over prior art, yielding the 250MS/s single-channel slope converter. A self-disabled comparator eliminates static leakage and consumes only 0.25pJ/conversion. A single calibration circuit corrects both offset errors and mismatches in...
This paper discusses the problem of object area detection of video frames. The goal is to design a pixel accurate detector for grass, which could be used for object adaptive video enhancement. A boosting neural network is used for creating such a detector. The resulted detector uses both textural features and color features of the frames.
A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented. Compared to traditional static-mismatch mapping and dynamic element matching, DMM reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty. This 0.14μm CMOS DAC achieves a state-of-the-art performance of SFDR>78dBc, IM3<;-83dBc...
This paper presents a flexible fully integrated self-calibrated quad-core 12-bit current-steering 180 nm CMOS DAC. Its novel architecture features multiple parallel sub-DAC unit cores. Their various combinations deliver smart flexibility in: performance, functionality, power management, design reuse, and smartness. The parallel sub-DAC units can be used together or separately to optimize the performance...
Timing errors become more dominant in dynamic performance in high-resolution Radio Frequency DACs. It consumes a lot of power and area to reduce timing errors below picoseconds. To relax the requirements on circuit design and layout complexity, a predictive timing error calibration technique based on on-chip timing error measurement is demonstrated in this work. Matlab behavior level simulation shows...
This paper analyzes and compares two open-loop track-and-hold architectures, both of which can be used as frontend sampling circuits for high-speed analog-to-digital converters. The first architecture is based on a source-follower, the second on a differential pair. Both theoretical analyses and simulation results are used to compare the alternatives with respect to speed, power consumption, accuracy,...
This paper presents a method for the on-chip measurement and correction of gain errors, offsets and time-skew errors in time-interleaved ADC's. With the proposed method, the errors can be measured and processed in the digital domain. Then, this information is used to optimize several digitally controlled analog parameters of the circuit, that minimize the effect of aforementioned mismatch errors....
This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of available operating modes (op-modes) can set the overall DAC performance and functionality. These op-modes transfer some of the important design trade-offs to the end-user and constitute the DAC flexibility. The main examples include:...
This paper presents a method for the on-chip measurement and correction of gain errors, offsets and nonlinearities of a track-and-hold circuit (T&H) of an ADC. Open-loop T&H circuits were considered in this paper because of their high-speed and low-power capabilities. However, these open-loop circuits require calibration for the aforementioned errors in order to achieve a high accuracy, especially...
Pipelined ADCs with open-loop residue amplifiers are currently gaining designers' attention due to the simplicity of their design, their low-power and/or high-speed capabilities and their improved deep-submicron compatibility. Although several studies on power optimization of pipelined ADCs with closed-loop amplifiers are reported in literature, none so far addresses the power optimization problem...
This paper presents the design of a digitally post-corrected open-loop front-end track-and-hold circuit for a pipelined ADC. An open-loop architecture has been selected to achieve high-speed and low power-consumption. Clock-boosting, resistive source-degeneration and cross-coupling are used to reduce low-order harmonic distortion. To further reduce distortion components in the open-loop circuit, a...
Timing errors become more and more important to dynamic performance in high-speed and high-resolution DACs. To relax the requirements on circuit design and layout complexity, two digital-delay-line (DDL) based calibration techniques for timing errors are demonstrated in this work. Matlab behavior level simulation results show that these two on-chip calibration techniques can improve the SFDR performance...
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