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It is well known that 3D channel devices, such as double-gate (DG) and tri-gate (TG) FinFETs, provide excellent short-channel effect (SCE) immunity. Thus, the scaled 3D channel FinFET flash memories with oxide-nitride-oxide (ONO) charge trapping layers have actively been developed [1–3]. Very recently, we have also developed floating-gate (FG) type SOI-FinFET flash memories [4–7]. In this paper, we...
The tri-gate (TG)- and double-gate (DG)-type poly-Si fin-channel split-gate flash memories with a thin n+-poly-Si floating-gate (FG) have successfully been fabricated, and their electrical characteristics including the variations of threshold voltage (Vt) and S-slope have been comparatively investigated. It was experimentally found that better short-channel effect (SCE) immunity, smaller Vt variations,...
The functional tri-gate flash memories with splitgate have been demonstrated for the first time, and its Vt variabilities before and after one P/E cycle have be systimetically compared with stack-gate ones. It was confirmed that split-gate shows smaller Vt distribution after erase and excellent over-erase immunity compared to those of stack-gate. Moreover, it was found that BVDS is higher than 3.2...
Free from the resolution limit, very narrow inverse taper structure of silicon wire could be fabricated with i-line photolithography. By covering the taper with a polyimide waveguide core, efficient coupling from optical fiber to silicon wire waveguide was possible.
PVD-TiN gate FinFET SRAM half-cells with different β-ratios and fin-height controlled transistors have successfully been fabricated using orientation-dependent wet etching and selective recess RIE. It was found that read static noise margin (SNM) increases significantly by controlling β from 1 to 2. With further increasing β, read SNM increases slightly. On the other hand, write margin shows weak...
The nanoscale TiN wet etching and its application for FinFET fabrication have been systematically investigated. It is experimentally found that the TiN side-etching can be controlled to be half of TiN thickness with precise time control. By using the developed nanoscale TiN wet etching technique, sub-30-nm physical gate length FinFETs, 100-nm tall fin CMOS inverters and SRAM half-cells have successfully...
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