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Conversion from dc to the 10th Nyquist band is enabled in a SHA-less, 10-b, 100-MS/s pipelined ADC by digitally calibrating the clock skew in the 3.5-b front-end stage. Architectural redundancy of pipelined ADC is exploited to extract skew information from the first-stage residue output with two out-of-range comparators and some simple digital logic; a gradient-descent algorithm is used to adaptively...
At high conversion speed, time interleaving provides a viable way of achieving analog-to-digital conversion with low power consumption, especially when combined with the successive-approximation-register (SAR) architecture that is known to scale well in CMOS technology. In this work, we showcase a digital background-equalization technique to treat the path-mismatch problem as well as individual ADC...
This paper presents a 6-bit, 1.2-GSample/s flash ADC with new proposed wideband track-and-hold amplifier (THA) fabricated in TSMC 0.13-mum CMOS technology. The wideband THA employs a front-end super source follower (SSF), which has a very low input capacitance of only 0.2-pf, to boost analog bandwidth without any on-chip passive inductor. Moreover, the flatness of the data bandwidth of ADC will improve...
This paper presents a 6-bit, 1.2-GSample/s flash ADC for MB-OFDM UWB receivers fabricated in TSMC 0.13-mum CMOS 1P8M process. Using a dedicated track-and-hold amplifier (THA) at front, it can eliminate different paths skew between comparators and clock jitter degradation to the comparators. Moreover, the proposed converter is designed with averaging and interpolation technique so that the offset of...
In this paper, the design techniques and considerations for each building block required for analog signal processing in HD-DVD PRML read channel are presented and the procedures of analog signal processing are also described. The analog front-end circuitry (AFE) includes the circuits of RF summer, attenuator, equalizer, AGC and ADC. The equalizer is constructed by seven-pole two-zero 0.05 degree...
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