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The downsizing of transistor dimensions enabled in the future nanotechnologies will inevitably increase the number of faults in the complex ULSI chips. To maintain the production yield at acceptable level, several levels of protection mechanisms will have to be implemented to tolerate the permanent and transient faults occurring in the physical layers. In this paper, we study fault tolerance at the...
We address two problems in this work, namely, 1) the resilience challenge in the future chips made up of massively defective nanoelements and organized in replicative multicore architectures and 2) the issue of preserving the production yield. Our main suggestion is that the chip should be self-configuring at the architectural level, enabling with almost no external control mechanisms, core mutual-test...
We describe a self-configuration methodology to tolerate defective nodes in chips organized in massively replicative architectures as those shown below in Figure 1, made up of hundreds of cores in a highly defective technology. Note that the keyword of this presentation is not configuration but self-configuration. The basic idea is that chips will become so complex that it will be unrealistic to consider...
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