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Subthreshold circuits are an ideal choice for ultra low power, moderate throughput applications. In subthreshold region to meet the ultra-low power requirement of energy constrained devices, supply voltage less than the threshold voltage is applied. At same frequency, subthreshold circuits show orders of magnitude power saving over superthreshold circuits. In subthreshold operating region, minute...
This paper investigates a robust 1-bit static full adder using FinFET at near-threshold region (NTR), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region provides minimum-energy point for the different frequency of operation with more favorable performance and variability characteristics. The proposed design features higher computing...
Optimization techniques for decreasing the time and chip area of adder circuits have been thoroughly studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we...
Optimization techniques for decreasing the time and chip area of adder circuits have been thoroughly studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we...
Optimization of power and speed is a very important issue in low-voltage and low-power applications. In this paper, a 1-bit full adder cell has been successfully analyzed by assigning high-threshold voltage to some transistors and low-threshold voltage to others. Moreover, a robust full adder circuit using dual threshold voltage MOSFETs (DT-MOS) has been proposed. The proposed design features lower...
This paper investigates subthreshold CMOS logic for ultra low power applications on next generation reconfigurable devices. The performance characteristics of key digital building blocks such as arithmetic units, multiplexers and look-up-tables have been analyzed in terms of speed, power dissipation and power delay product using Berkeley predictive technology models at 22 nm technology node for both...
Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power CMOS, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs...
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