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In the paper, a technique for design of highly dependable communication structure in SRAM-based FPGA is presented. The architecture of the multicore system and the structure of fault tolerant bus with cache memories are demonstrated. The fault tolerant properties are achieved by the replication and utilization of the self checking techniques together with partial dynamic reconfiguration. The experimental...
In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller...
In the paper, the methodology of fault tolerant systems design based on field programmable gate array are presented. The architectures are based both on duplex and triple modula redundancy systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in triple modula redundancy and...
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of communication protocols, counters, decoders, registers, comparators, etc. It is also demonstrated how a checker for more complex structures can be developed. We describe the possibilities of utilizing this approach in the design...
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be performed - in the paper the lowest level is presented. The definition of dedicated language for the description of possible communication faults is presented. The core generator is used to produce VHDL code describing the...
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