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Turbo codes facilitate near-capacity transmission throughputs by achieving a reliable iterative forward error correction. However, owing to the serial data dependence imposed by the logarithmic Bahl–Cocke–Jelinek–Raviv algorithm, the limited processing throughputs of the conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time communication schemes...
This paper develops a novel path planning algorithm using improved ant colony optimization (ACO) and its FPGA implementation. The proposed approach can effectively increase the accuracy to generate an optimal path. The main idea of this paper is to avoid local minimum by continuous tuning of a setting parameter and the establishment of new mechanisms for opposite pheromone updating and partial pheromone...
This paper presents a hardware/software co-design method for a hybrid object tracking algorithm incorporating particle filter (PF) and particle swarm optimization (PSO) based on System On Program Chip (SOPC) technique. Considering both the execution speed and design flexibility, we use a embedded processor to calculate weight for each particle and a hybrid accelerator implemented by hardware to update...
This paper proposed a speed controller design for a DC motor by using a FPGA chip and applies it on a wheeled robot. For the motor accelerating control, this paper proposed a hardware PI controller circuit module to achieve the accelerating control. On the motor decelerating control, this paper proposed a braked deceleration circuit module to improve the skid of tires when the wheel-type robot brakes...
In this paper, a Hardware/Software (HW/SW) co-design method of ant colony optimization (ACO) algorithm is proposed to implement on the FPGA chip. In this paper, the software is designed with C language and hardware is designed with Verilog hardware description language (HDL). The HW/SW co-design method is a technique based on a SOPC (System on a Programmable Chip). In this paper, the path selecting...
This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve the performance of particle swarm optimization (PSO) for embedded applications. Based on modular design architecture, a particle updating accelerator module via hardware implementation for updating velocity and position of particles and a fitness evaluation module implemented...
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