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In this paper, based on the temperature calculation in block-level thermal model, a two-phase approach is proposed to reduce the final floorplan temperature by redistributing the white space in all the device layers and inserting the thermal vias onto the available white space. The experimental results show that our proposed approach reduces 5.5%, 11.3% and 20.5% of temperature on 100%, 110% and 120%...
Given a set of connecting nodes in a signal net with a set of obstacles on different layers for 3D ICs, based on the refinement of minimum routing region and the concept of hidden Steiner-point assignment on the same layer or different layers, a merging-based approach is proposed to construct a timing-driven 3D rectilinear Steiner tree with obstacle avoidance. Compared with a spanning-tree-based approach,...
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