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Junction engineering solutions are presented in this work to improve the triggering and performance of SCR devices in an advanced 22nm SOI CMOS technology. Several SCR cathode junction formations are investigated including implants energy, dosage, with or without halo/extension implants. TLP and HBM results are presented in details.
We present DC and TLP data of four-terminal SCR devices and a diode-triggered SCR from an advanced SOI CMOS technology. Data analysis concludes that the triggering of an actively triggered SCR is related only to the current gain of each individual bipolar transistor, not the current gain product. Successful current sustaining of the SCR depends on the base resistance of its passively triggered bipolar...
We present for the first time an ESD protection strategy using silicide-blocked PMOSFETs to improve negative-mode external latchup robustness by eliminating N+ junctions directly connected to the I/O pad. 100 ns TLP data of thin (Tox=1.25 nm) and thick oxide (Tox = 5.2 nm) silicide-blocked PMOSFETs in a 65 nm CMOS technology show failure currents of ~6 mA/mum and ~5 mA/mum respectively, suitable for...
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