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A non-self protection ESD scheme using grounded-gate, gate non-silicided (GG-GNS) drain/source silicide blocked (SBLK) ESD NFET offered in 45 nm SOI CMOS technology is presented based on a comprehensive study using the high current pulse characteristics. The results show that with a minimum SBLK width over drain/source, GG-GNS NFET can handle ~3.4 mA/mum current.
We present for the first time an ESD protection strategy using silicide-blocked PMOSFETs to improve negative-mode external latchup robustness by eliminating N+ junctions directly connected to the I/O pad. 100 ns TLP data of thin (Tox=1.25 nm) and thick oxide (Tox = 5.2 nm) silicide-blocked PMOSFETs in a 65 nm CMOS technology show failure currents of ~6 mA/mum and ~5 mA/mum respectively, suitable for...
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