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Challenges of electrostatic discharge (ESD) protection in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O MOSFETs, interconnect, ESD protection and power clamp devices. Recent progress on ESD protection design for both high-speed digital I/O and radiofrequency (RF) circuits are presented. Topological trade-offs are compared. High speed circuit...
The double well field effect diode (DWFED), an SOI SCR-like device for ESD protection of I/O circuits, is presented. The effect of device and process parameters on the diode on-voltage is examined, and the TLP and VFTLP characteristics of the DWFED are compared with those of the SOI lateral diode. It is shown how to use the DWFED for local clamping ESD protection, with a diode-like It2 level.
In this paper the authors present the field effect diode (FED) as a novel device with a new approach for ESD protection in SOI. Device parameters are identified and optimized to achieve optimum ON and OFF behavior. Furthermore, the authors present two ways the FED can be used in an ESD protection scheme: in I/O clamping and in a high-voltage supply clamp
It is crucial to minimize the parasitic capacitance at a high-frequency I/O, found in applications such as high-speed serial links and radio receivers. Here, we study the bias-dependent capacitance of a poly-defined SOI diode-a popular ESD protection device according to C. Putnam et al. (2004), C. Entringer et al. (2005), M. Khazbinisky et al. (2005), S. Mitra et al. (2005), and S. Voidman et al....
We study the SOI poly-defined lateral diode and its optimization to achieve high second breakdown current, low resistance and low capacitance. A second breakdown current of more than 12 mA/mum is achieved. We present a novel failure mechanism for the diode wherein oxide breakdown occurs during a CDM-like event; floating the poly gate is shown to reduce this susceptibility. We also introduce a biasing...
In this paper we will present a new integrated SOI substrate diode structure for ESD protection of SOI I/O circuits that is built under the buried oxide of the SOI wafer using a standard CMOS process. We will show that the protection level can reach four times what is achieved by the standard-lateral SOI diode structure. We will also show device and process simulation results to understand the self-heating...
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