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A complete frequency synthesizer occupying 1.1 mm2 in 65 nm CMOS is presented. It is composed of a push-push quadrature VCO that delivers two L0 signals in 20 and 40 GHz bands. The PLL consumes 80 mW including buffers, and achieves a phase noise lower than -100 and -97.5 dBc/Hz for the 20 GHz and the 40 GHz signals, respectively.
A DVB-T tuner is integrated in 0.12 /spl mu/m CMOS. The 16mm/sup 2/ chip integrates a double conversion chain including PLL, VCO, voltage regulators, and ADC. The receiver exhibits a 6.5dB NF, a VCO phase noise of -140dBc/Hz at 1MHz offset at 1.21GHz, and a 14b ADC. It is compatible for integration with a digital demodulator IP.
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