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Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12??) for BE nFET devices to-date, consistent with simulations showing the need for ≪14??...
A wide dynamic-range (DR) pixel-level CMOS image sensor with self-reset technique has been fabricated using a 0.18-mum six-metal CMOS technology and tested to verify simultaneous increase of both DR and peak signal-to-noise ratio (SNR). It provides a continuous peak SNR enhancement over a strong incident light range. Maximum achievable DR is measured over 71.1 dB, and SNR keeps increasing at 7.3 dB/decade...
This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated...
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