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Most of the high speed low power ADCs are interleaved using calibration which have some drawback like calibration time, the complexity associated with calibration algorithm and its circuit implementation. Therefore a single channel calibration-free 12-bit ADC sampling at 600MS/s in 28nm UTBB FDSOI is presented. Selected ADC architecture of mixing Pipelined stage and Asynchronous SAR demonstrates advantages...
A large number of routing protocols for Cognitive radio networks (CRNs) have been proposed recently, each based on different design goals, and evaluated in different scenarios, under different assumptions. In our previous work, we conducted the first extensive empirical performance study of routing protocols for CRNs-Coolest Path, SAMER, and CRP — under the same realistic set of assumptions. Our study...
This paper presents the design of microstrip slot antenna in order to investigate bandwidth enhancement with better return loss. It is observed that the impedance bandwidth can be improved through various slot configurations in microstrip patch antenna. In this study three slots of 25 mm2, 51.5mm2 and 276 mm2 are considered on the ground plane for bandwidth enhancement. It is observed that the addition...
Sleep and Idle modes are proposed as power saving mechanisms in IEEE 802.16j Mobile Multi-hop Relay (MMR) networks. In this paper, these mechanisms are analyzed in terms of number of messages exchanged, latency and cost. Besides, hybridization of Sleep and Idle modes, named as Torpid mode is proposed as a power saving mechanism for IEEE 802.16j. Our proposed mechanism takes advantage of the relay...
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